This blog describes the execution command and results for running the SPEC 2017 benchmark on QEMU user mode which, itself, runs on an architecture that is not RISC-V and is used for running a single binary compiled for RISC-V.
This benchmark is run on qemu-riscv64 version 8.2.1 running on ubuntu 22.04 LTS on x86.
The environment is an LXC container which is allocated 4 cores of AMD EPYC™ 7713, 8GB of memory, and 2GB of swap.
Source code modifications
Usually, the SPEC benchmark is run in such a way that the user executes a single bash script which in turn calls perl scripts and those perl scripts call other relevant scripts.
The issue with this approach is that, for running a binary on a QEMU user-mode, the binary should be compiled for RISC-V architecture and should be present on architecture other than RISC-V (x86 in this case). For this to work, every binary that SPEC CPU 2017 creates during the execution of the test should be compiled for RISC-V architecture and should execute on QEMU instead of native architecture.
For this purpose, I had to tweak the harness of SPEC CPU 2017, so that the execution command prepends qemu-riscv64 -L <test_to_execute>.
*If you need information or help regarding how this can be done, contact cloud-v@10xengineers.ai*
Execution of tests
The execution command is not the same as that of previous tests. I had to run tests without the reportability flag and without peak settings of compiler. The test command is as follows.
./runcpu --threads=1 --copies=1 --config="/home/user1/gcc-linux-qemu-riscv64.cfg" <list_of_space_separated_test_names>
I used this command and added all test names separated by space.
Results
Individual Test Results
The individual test results of qemu-riscv64 with single thread are as follows:
Final Results (comparison with physical hardware)
The following results of other instances are taken out from the previous SPEC CPU intrate/multicore blog.
Conclusion
These results show us that qemu-riscv64 user mode emulator is even faster than qemu-system-riscv64 and with latest specification changes even in single core performance. This makes the RISC-V software development streamlined and even faster on emulated RISC-V compute instances.
